1. Field of the Invention
The present invention relates to a field-effect-type semiconductor device. More particularly, it relates to a field-effect-type semiconductor device of which short-circuit current is reduced without sacrificing ON-resistance.
2. Description of Related Art
There have conventionally been used field-effect-type semiconductor devices for power supply (e.g., an insulated gate-type bipolar transistor disclosed in Japanese Laid-Open Patent Publication No. 2002-100770). Some conventional field-effect-type semiconductor devices of this type apply ladder-type emitter structure aiming to reduce ON-resistance. FIG. 30 and FIG. 31 show an example of that. FIG. 31 is a sectional view of a portion B—B in FIG. 30. FIG. 30 is a sectional view of a portion A—A in FIG. 31. The sectional view of the portion C—C in FIG. 30 is substantially same as FIG. 3 of which numberings are changed from “1**” to “9**”. This field-effect-type semiconductor device is so-called a trench-gate type. The field-effect-type semiconductor device is generally structured such that an emitter region and gate electrodes are arranged at a surface side of its semiconductor substrate (upper side in FIG. 31) and a collector region is arranged at the reverse side (lower side in FIG. 31 and FIG. 3).
That is, there are arranged trench-structured gate electrodes 906, a P+ emitter region 900, and an N+ emitter region 904 at the surface side of the semiconductor substrate. The gate electrodes 906 are insulated from the semiconductor substrate by a gate dielectric 905 and an interlayer dielectric 907. An emitter electrode 909 is arranged above the interlayer dielectric 907. The emitter electrode 909 is in contact with both the P+ emitter region 900 and the N+ emitter region 904. A P channel region 903 is arranged below those emitter regions. The bottom portion of the P channel region 903 is shallower than that of the gate electrodes 906.
An N drift region 902 is formed below the P channel region 903. Most part of the N drift region 902 is deeper than the bottom portion of the gate electrodes 906 and extends to almost entire plane of the semiconductor substrate. A P+ collector region 901 is arranged further below the N drift region 902. A collector electrode 910 is formed in contact with the bottom portion of the P+ collector region 901. In this field-effect-type semiconductor device, a range indicated with an arrow Y is a unit repeated in a vertical direction in FIG. 30.
In this field-effect-type semiconductor device, as shown in FIG. 30, the gate electrodes 906 and the N+ emitter region 904 are arranged alternately in vertically-striped pattern. The P+ emitter region 900 is insularly arranged with being surrounded by the N+ emitter region 904. Therefore, N+ emitter region 904 is arranged like a ladder pattern in FIG. 30. Furthermore, a width of the P+ emitter region 900 in FIG. 30 is narrower than a width 908 that is the width of a portion where the emitter electrode 909 is in contact with the P+ emitter region 900 and the N+ emitter region 904. A width 908 will be termed as a “contact aperture 908” hereinafter.
In this field-effect-type semiconductor device, current between the emitter electrode 909 and the collector electrode 910 is controlled by applying voltage to the gate electrodes 906. That is, conduction type around the surface of the P channel region 903 facing to side walls of the gate electrode 906 is reversed by voltage of the gate electrodes 906 thereby to form a current path. The N+ emitter region 904 is a ladder-patterned region. Therefore, when being inverted, a surface of the P channel region 903 becomes an effective channel with either a portion including the P+emitter region 900 (portion B—B in FIG. 30, i.e., a portion cross section of which is shown in FIG. 31) or a portion without P+ emitter region 900 (portion C—C in FIG. 30, i.e., a portion cross section of which is shown in FIG. 3). That is, the entirety of units Y repeated in a vertical direction (see FIG. 30) is a channel width. A channel width is thus taken as large as possible so as to reduce ON-resistance.
However, the above-described conventional field-effect-type semiconductor device has had the following problems.
A first problem is that short-circuit current is excessive. Such excessive short-circuit current is caused by the following mechanism: when short-circuiting occurs under ON state, large amount of electrons are supplied to the N drift region 902 from the N+ emitter region 904 through the N channel of the P channel region 903 and along with that, large amount of holes are supplied to the N drift region 902 from the P+ collector region 902. Short-circuit current under such situation is larger than ten-times of ON current under normal operation state. Therefore, a semiconductor device is heated to destroy with sudden overheating. On the other hand, from the viewpoint of normal operation state, ON current is less than one-tenth of short-circuit current. This means that only one-tenth or fewer amounts of electrons that can be supplied from the channel are actually used under normal operation state. Subsequently, the widened channel width does not work out efficiently. Accordingly, ON-resistance is not very low in fact.
A second problem is that latch-up phenomenon is likely to occur under OFF state. That is, since the N+ emitter region 904 is ladder patterned, a contact area of P-type region and the emitter electrode 909 (i.e., an area for a P+ emitter region 900 in FIG. 30) is small. Therefore, an escape path for holes in the P channel region 903 to escape to the emitter electrode 909 is narrow. Thereby, holes are likely to remain in the P channel region 903 after switching to OFF state, especially, after large current such as short-circuit current is turned off. This phenomenon is same as a situation such that base current flows into a parasitic bipolar transistor constituted by the N+ emitter region 904, the P channel region 903, and the N drift region 902. Therefore, a parasitic NPNP thyristor constituted by the N+ emitter region 904, the P channel region 903, the N drift region 902, and the N+ collector region 901 is turned on. As a result, latch-up phenomenon occurs. Current control is impossible under latch-up phenomenon occurring situation, whereby device is destroyed.
It is conceivable to constitute an emitter with only a P+ emitter region of which impurity concentration is high so as to avoid latch-up phenomenon. However, with such emitter structure, conduction type of the P+ emitter region cannot be reversed. Therefore the following problems are caused. Firstly, since supply of electrons to the N drift region 902 becomes inconstant, current flowing in device becomes unstable. This causes latch-up phenomenon in a high current region. Furthermore, since impurity concentration of the P+ emitter region is high, it is low resistance. Furthermore, the contact area of the P+ emitter region and the emitter electrode 909 is significantly large. Therefore, holes in the N drift region 902 escape to the emitter electrode 909 through the P+ emitter region. This causes shortage of holes in the N drift region 902 and results in high ON resistance.